+; register defs
+
+#define SCRNW 159
+#define SCRNH 143
+
+; lcd registers
+
+; lcd y
+#define RLY 0xFF44
+#define RLYC 0xFF45
+#define RLCD 0xFF40
+
+#define LCDCF_BGON 0b00000001
+#define LCDCF_ON 0b10000000
+#define LCDCF_OBJON 0b00000010
+#define LCDCF_TILE_BANK 0b00010000
+#define LCDF_WINDOWON 0b00100000
+#define LCDF_OBJ_SIZE 0b00000100
+#define LCDF_WINBANKSELECT 0b01000000
+
+#define RSTAT 0xFF41
+
+#define STATF_LYC_INT_SELECT 0b01000000
+
+#define RBGP 0xFF47
+#define ROBP0 0xFF48
+#define ROBP1 0xFF49
+
+; screen scroll y and x
+#define RSCY 0xFF42
+#define RSCX 0xFF43
+
+; window y and x
+#define RWY 0xFF4A
+#define RWX 0xFF4B
+
+; P1: joy pad register
+#define RP1 0xFF00
+#define P1F5 0b00100000 ; get buttons
+#define P1F4 0b00010000 ; get dpad
+
+; buttons
+.def int BTNDOWN = 0x80
+.def int BTNUP = 0x40
+.def int BTNLEFT = 0x20
+.def int BTNRIGHT = 0x10
+.def int BTNSTART = 0x08
+.def int BTNSELECT = 0x04
+.def int BTNA = 0x01
+.def int BTNB = 0x02
+
+; obj off-screen offsets
+#define OBJ_OFF_X 8
+#define OBJ_OFF_Y 16
+
+; interrupts
+; interrupt flag
+#define IF 0xFF0F
+; interrupt enabled
+#define IE 0xFFFF
+#define IVBLANK 0b00000001
+#define ILCD 0b00000010
+
+; location where code for dma needs to be memcyp'd to
+.def int DMAFN = 0xFF80
+#define DMA 0xFF46
+
+#define OBJSMAX 40
+
+.def int P1FDPAD = P1F5
+.def int P1FBTN = P1F4
+.def int P1FNONE = P1F5 | P1F4
+
+; memory map
+.def int VRAM = 0x8000
+.def int VRAM8800 = VRAM+0x0800
+.def int VRAM9000 = VRAM+0x1000
+
+.def int VIEW_W = 20
+.def int VIEW_H = 20
+.def int SCRN_W = 32
+.def int SCRN_H = 32
+
+.def int SCRN0 = 0x9800
+.def int SCRN0_UI = SCRN0 + SCRN_W * 16
+
+.def int SCRN1 = 0x9C00
+.def int OAMRAM = 0xFE00
+.def int OBJSIZE = 4
+.def int OAMRAM_SIZE = OBJSMAX * OBJSIZE
+
+.def int OAM_FPRIO = 0b10000000
+#define OAM_FYFLIP 0b01000000
+#define OAM_FXFLIP 0b00100000
+#define OAM_DMG_PAL 0b00010000
+
+; MBC1 registers
+
+; write 0xA here to enable sram
+#define MBC1_SRAM_ENABLE 0x0000
+#define MBC1_ROM_BANKSEL 0x2000
+#define MBC1_SRAM_BANKSEL 0x4000
+
+; audio registers
+#define AUDIO_CTRL 0xFF26
+#define MASTER_VOLUME 0xFF24
+
+#define CH1_SWEEP 0xFF10
+#define CH1_LEN_DUTY 0xFF11
+#define CH1_VOL_ENV 0xFF12
+#define CH1_PERIOD_LO 0xFF13
+#define CH1_PERIOD_HI_CTRL 0xFF14
+
+#define CH4_LENGTH 0xFF20
+#define CH4_VOLUME_ENV 0xFF21
+#define CH4_FREQ_RAND 0xFF22
+#define CH4_CTRL 0xFF23
+
+#define AUDIO_ALL_ON 0b10000000
+#define AUDIO_ALL_OFF 0b00000000
+
+