srl $1 ; / 2
srl $1 ; / 4
srl $1 ; / 8
+#endmacro
+
+ ; divides a regiser by 16
+ ; inputs:
+ ; $1: the register
+#macro div8
+ srl $1 ; / 2
+ srl $1 ; / 4
+ srl $1 ; / 8
+ srl $1 ; / 16
#endmacro
; multiplies a regiser with 8
sla $1 ; * 8
#endmacro
+ ; multiplies a regiser with 16
+ ; inputs:
+ ; $1: the register
+#macro mul16
+ sla $1 ; * 2
+ sla $1 ; * 4
+ sla $1 ; * 8
+ sla $1 ; * 16
+#endmacro
+
; asserts. if $1 != $2 causes a ld b, b
; inputs:
; $1: comparison (z, nz, c, nz)