From: Lukas Krickl <lukas@krickl.dev>
Date: Fri, 24 Nov 2023 10:33:56 +0000 (+0100)
Subject: Added more instructions
X-Git-Url: https://git.krickl.dev/?a=commitdiff_plain;h=2d36c7970af524124a3bd66581f6c7d985436950;p=ulas%2F.git

Added more instructions
Added test code
---

diff --git a/src/ulas.c b/src/ulas.c
index cbe7e0c..8c32c79 100644
--- a/src/ulas.c
+++ b/src/ulas.c
@@ -1088,7 +1088,6 @@ end:
   return tokrc;
 }
 
-
 /**
  * Parse expressions from tokens
  * return tree-like structure
@@ -1405,12 +1404,19 @@ int ulas_asmregisr8(enum ulas_asmregs reg) {
   return reg != ULAS_REG_BC && reg != ULAS_REG_DE && reg != ULAS_REG_HL;
 }
 
+/**
+ * Instruction table
+ */
+
 // define <name> r8, r8
 #define ULAS_INSTR_R8R8(name, base_op, reg_left, reg_right)                    \
   {                                                                            \
     (name), {(reg_left), ',', (reg_right), 0}, { base_op, 0 }                  \
   }
 
+#define ULAS_INSTR_R16R16(name, op, reg_left, reg_right)                       \
+  ULAS_INSTR_R8R8(name, op, reg_left, reg_right)
+
 #define ULAS_INSTR_R8R8D(name, base_op, reg_left)                              \
   ULAS_INSTR_R8R8(name, base_op, reg_left, ULAS_REG_B),                        \
       ULAS_INSTR_R8R8(name, base_op + 1, reg_left, ULAS_REG_C),                \
@@ -1471,11 +1477,20 @@ const struct ulas_instr ULASINSTRS[] = {
     ULAS_INSTR_R8_EXPR8("ld", 0x06, ULAS_REG_B),
     ULAS_INSTR_R8_EXPR8("ld", 0x16, ULAS_REG_D),
     ULAS_INSTR_R8_EXPR8("ld", 0x26, ULAS_REG_H),
+
+    // ld [r16], a
     {"ld", {'[', ULAS_REG_HL, ']', ',', ULAS_E8, 0}, {0x36, ULAS_E8, 0x00}},
     {"ld", {'[', ULAS_REG_BC, ']', ',', ULAS_REG_A, 0}, {0x02, 0}},
     {"ld", {'[', ULAS_REG_DE, ']', ',', ULAS_REG_A, 0}, {0x12, 0}},
     {"ld", {'[', ULAS_REG_HL, '+', ']', ',', ULAS_REG_A, 0}, {0x22, 0}},
     {"ld", {'[', ULAS_REG_HL, '-', ']', ',', ULAS_REG_A, 0}, {0x32, 0}},
+
+    // ld a, [r16]
+    {"ld", {ULAS_REG_A, ',', '[', ULAS_REG_BC, ']', 0}, {0x0A, 0}},
+    {"ld", {ULAS_REG_A, ',', '[', ULAS_REG_DE, ']', 0}, {0x1A, 0}},
+    {"ld", {ULAS_REG_A, ',', '[', ULAS_REG_HL, '+', ']', 0}, {0x2A, 0}},
+    {"ld", {ULAS_REG_A, ',', '[', ULAS_REG_HL, '-', ']', 0}, {0x3A, 0}},
+
     {"ld", {'[', ULAS_E16, ']', ',', ULAS_REG_SP, 0}, {0x08, ULAS_E16, 0}},
 
     // ld r16, e16
@@ -1487,6 +1502,9 @@ const struct ulas_instr ULASINSTRS[] = {
     // jr
     ULAS_INSTR_R8_EXPR8("jr", 0x20, ULAS_REG_NOT_ZERO),
     ULAS_INSTR_R8_EXPR8("jr", 0x30, ULAS_REG_NOT_CARRY),
+    {"jr", {ULAS_E8, 0}, {0x18, ULAS_E8, 0x00}},
+    ULAS_INSTR_R8_EXPR8("jr", 0x28, ULAS_REG_ZERO),
+    ULAS_INSTR_R8_EXPR8("jr", 0x38, ULAS_REG_CARRY),
 
     // inc/dec
     ULAS_INSTR_REG("inc", 0x03, ULAS_REG_BC),
@@ -1504,6 +1522,11 @@ const struct ulas_instr ULASINSTRS[] = {
     ULAS_INSTR_REG("dec", 0x25, ULAS_REG_H),
     {"dec", {'[', ULAS_REG_HL, ']', 0}, {0x35, 0x00}},
 
+    ULAS_INSTR_REG("dec", 0x0B, ULAS_REG_BC),
+    ULAS_INSTR_REG("dec", 0x1B, ULAS_REG_DE),
+    ULAS_INSTR_REG("dec", 0x2B, ULAS_REG_HL),
+    ULAS_INSTR_REG("dec", 0x3B, ULAS_REG_SP),
+
     // alu r8, r8
     ULAS_INSTR_ALUR8D("add", 0x80),
     ULAS_INSTR_ALUR8D("adc", 0x88),
@@ -1514,6 +1537,12 @@ const struct ulas_instr ULASINSTRS[] = {
     ULAS_INSTR_ALUR8D("or", 0xB0),
     ULAS_INSTR_ALUR8D("cp", 0xB8),
 
+    // alu r16, r16
+    ULAS_INSTR_R16R16("add", 0x09, ULAS_REG_HL, ULAS_REG_BC),
+    ULAS_INSTR_R16R16("add", 0x19, ULAS_REG_HL, ULAS_REG_DE),
+    ULAS_INSTR_R16R16("add", 0x29, ULAS_REG_HL, ULAS_REG_HL),
+    ULAS_INSTR_R16R16("add", 0x39, ULAS_REG_HL, ULAS_REG_SP),
+
     {NULL}};
 
 // assembles an instruction, writes bytes into dst
diff --git a/test/t0.s b/test/t0.s
new file mode 100644
index 0000000..78cff3f
--- /dev/null
+++ b/test/t0.s
@@ -0,0 +1,29 @@
+; this is a sample assembly file 
+; that can be read by tests
+.org 0x100 ; comment
+  nop
+  ; full line is a comments
+  halt ; comment
+  stop
+  di
+  ei
+
+  ld c, a
+  ld b, [hl]
+  adc a, c
+  ld b, 6 + 2 ; comment after expression 
+  jr nz, 2 + 2
+
+  ld sp, 0x100 + 0x21A
+  ld [hl+], a
+  inc hl
+  inc [hl]
+  ld [hl], 1
+  ld [1 + 2], sp
+  jr -2
+  add hl, bc
+
+  ld a, [bc]
+  ld a, [hl+]
+
+  dec bc